1. Field of the Invention.
The invention relates to junction field effect transistors and more particularly junction field effect transistors suitable for integration with bipolar transistors into integrated circuits.
2. Description of the Prior Art.
Junction field effect transistor ("JFET") structures suitable for use in monolithic integrated circuits are known in the art. Integrated circuits incorporating both bipolar junction transistors and JFETs have highly desirable characteristics, and accordingly processes have been developed which are compatible with the fabrication of both types of devices in a single integrated circuit. Preferably, these processes involve a minimum number of dopant diffusion and implantation steps.
Minimization of the number of steps in a process has typically involved using a particular diffusion or implantation step to simultaneously form structures required in each device. A bipolar junction transistor has base, emitter and collector regions. A JFET has gate, channel, source and drain regions. Frequently, a JFET is a symmetric device and the drain and source regions are indistinguishable until connected into a circuit. Where the base region of the bipolar device is of a like conductivity type with the source/drain regions of the JFET, all three regions can be produced in a single diffusion or implantation step.
Location of various diffused or implanted regions in an integrated circuit is controlled by exposing only selected portions of the surface of the semiconductor material to diffusion or ion implantation by well known processes. Masks are used to control exposure of photoresist layers laid over the surface of the semiconductor to actinic radiation. After development of the photoresist layer exposes the desired portions of the semiconductor surface, the appropriate diffusion or implantation step is taken. Each implantation step involves a number of substeps.
It is also desirable to achieve a device of a minimum size. Benefits which accrue with size reduction include faster devices and the ability to put more devices into a given area on the semiconductor die. As described above, there are four regions generic to JFETs. Minimization of the size of the overall device depends on reduction in the size of these regions. However, a number of factors come into play when a given region is reduced in size.
Reference to U.S. Pat. No. 4,176,368 by Compton highlights certain of these factors. Compton teaches a p channel JFET suitable for incorporation with bipolar transistors in an integrated circuit. A JFET gate region comprises a portion of a lightly doped n conductivity type epitaxial layer isolated within a p type region over a substrate. The gate region also includes a highly conductive buried layer underlying active regions of the device to enhance gate conductivity. Two symmetric, diffused moderately doped p type regions are provided at spaced apart intervals over the buried layer within the gate region to provide a source and a drain. The source/drain diffusion is compatible with formation of base regions for npn bipolar transistors elsewhere on the device surface.
Compton provides a single lightly doped p type subsurface channel for connecting the diffused source and drain regions. The transconductance requirements of the JFET are met by varying the width of the channel. Between the subsurface channel and the surface of the semiconductor device are implanted subregions of the gate region including a moderately doped n type cap and a heavily doped n type top gate. The top gate overlaps the lateral bounds of the channel to provide a low resistance electrical path from the pn junction between the top gate and the channel to the buried layer. The moderately doped caps space the top gate from the source and drain regions to avoid creation of a pn junction between these relatively heavily doped regions which would be characterized by a low reverse breakdown voltage.
A gate electrode in Compton's device is attached to a heavily doped n type diffusion region, which provides a low resistance connection between an electrode and the gate region. Operation of the JFET is conventional, a voltage is applied to the gate region by the gate electrode to reverse bias the pn junctions between the gate region and the source, drain and particularly the channel regions. As the reverse bias voltage is increased, depletion regions adjacent the pn junctions expand, eventually cutting off the channel region beneath the top gate. Doping of the top gate is selected so that a space charge region develops under reverse bias voltage into the channel primarily from its junction with the top gate. To provide a reasonably high speed device, the current path through the top gate to the gate electrode must be highly conductive. Notwithstanding high conductivity, frequency response of the Compton device in A.C. operation is affected by the distance the gate current must travel. Charge taken from or transmitted to the space charge region adjacent the top gate passes laterally across the width of the top gate. The charge travels between the highly conductive buried layer and the top gate around the lateral bounds of the channel. The heavily doped region adjacent the gate electrode provides a low resistance path for the gate charge. A space charge region also develops under reverse bias adjacent the deeper junction between the gate and the channel. Charge moves directly between this junction and the buried layer under reverse biasing. The lower space charge region which develops provides a relatively small part of the total pinch-off effect.
Several disadvantages are associated with the Compton device. The top gate must be made highly conductive to compensate for delays introduced because of its width. The wider the top gate is made, to allow for higher transconductance JFETs, the more heavily doped the top gate must be to maintain a given response speed. Fabrication of a bounded top gate is also a complicated process requiring three separate maskings of the device to produce the channel, the cap and the top gate.